Cache TAGs have been found to substantially enhance performance of a processing system. The processing system has a processor which generates addresses which are requests for instructions or data. A cache TAG determines if the requested instruction or data is present in a cache memory which can rapidly provide the requested instruction or data. The cache TAG bases this determination upon the address which is provided by the processor. There may be more than one cache TAG integrated circuit used for this determination in which each cache TAG receives a portion of the provided address. The portion of the address received by each cache TAG integrated circuit is further divided into an index portion and a TAG portion. Normally, the index portion is common to all of the cache TAGs, and the TAG portion is unique to each cache TAG. Each cache TAG is substantially like a typical static random access memory (SRAM) in which the index portion acts like the address of the memoroy to which the memory responds by providing one or more bits of data which are compared to the TAG portion of the address. The data provided by the cache TAG is not the same as that requested by the processor. The present invention is directed to a cache TAG so that "data" as used herein will relate to the TAG portion of the address either as applied to the cache TAG or as provided by the cache TAG in response to an index. The whole address, which typically includes the index and all of the TAGs and may include some other information such as specific byte information, will be referred to as the system address. Information which is provided in response to the system address will be called "system data" and can include instructions.
In response to the index then, the cache TAG internally provides data comprised of a predetermined number of bits which are compared to the TAG portion of the address of a like number of bits. If the comparison indicates that they are the same, a match (or hit) signal is generated by the cache TAG. The performance of the cache TAG is to a large extent judged by the speed with which the cache TAG can provide the proper logic state of the match signal. There are two common specifications for stating this performance characteristic. The first is address valid to match valid (AVMV). The second is data valid to match valid (DVMV). The AVMV specification is for the case in which only the index is changed, i.e., data (the TAG) is not changed. The DVMV is for the case when only the data is changed, i.e., the address (the index) is not changed. The AVMV is always slower than the DVMV because a change in address requires an access to the array whereas a change in data does not. Thus, in general, the AVMV has been the limit in speed. Some processing systems have been designed to take advantage of the faster DVMV specification. Such designs introduce logic in the data path which causes some additional delay for that path. As the cache TAGs have developed even faster speeds, the difference between the AVMV and DVMV has typically gotten to be less to the point where the added delay in the system exceeds the difference between AVMV and DVMV. In such a processing system then the data change is the slower cache access. Thus it is desirable that both the AVMV and DVMV specifications be optimized.
One of the functions which must be performed by a cache TAG is a compare of the data which is performed in a compare mode. There may be more than one compare mode. This compare function has been achieved with exclusive NOR logic which adds delay. The comparator which performs this function is in the critical path to the match output. Thus, any delay added by the comparator adds the same delay to the AVMV and DVMV specifications. Thus any reduction in the delay of the comparator improves both the AVMV and DVMV specifications. The number of exclusive NOR comparators is equal to the number of bits of data. Each exclusive NOR comparator thus determines if the single bit of data to which it corresponds is a match. There is then also a further determination that all of the bits, which correspond to the particular cache TAG, match before the match signal is generated by that cache TAG. This match comparator which generates the match signal is also in the critical speed path. Another function which must also must be performed quickly is an output of the data which is provided in a read mode. This is a different mode of operation from the compare mode. The output of data in response to an address is also an important specification for which it is desirable that the compare function not impede. This has resulted in the read path (the data out path) divert from the compare path before reaching the comparator.
Another function which it has been found desirable to provide is an and/or/invert function. This has been useful for providing flexibility to the integrated circuit. In a processing system which has a cache, not only must the system address be compared but there must also be verification that the stored system data is valid. The cache system includes circuitry for providing valid bits to indicate if the stored system data which corresponds to the matched system address is valid. The and/or/invert function provides for this capability. This aids the manufacturer of the processing system by reducing the number of different integrated circuit types required for making the processing system. In providing this and/or/invert function, it is also desirable that no additional time be added to the read and compare functions.